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LHF08CTE
21
Start
Write 60H,
Block/Device Address
Write 01H/F1H,
Block/Device Address
Bus
Operation
Write
Write
Command
Set
Block/Master
Lock-Bit Setup
Set
Block or Master
Lock-Bit Confirm
Comments
Data=60H
Addr=Block Address(Block),
Device Address(Master)
Data=01H(Block),
F1H(Master)
Addr=Block Address(Block),
Device Address(Master)
Read
Status Register
Read
Status Register Data
SR.7=
0
Standby
Check SR.7
1=WSM Ready
0=WSM Busy
1
Repeat for subsequent lock-bit set operations.
Full Status
Check if Desired
Full status check can be done after each lock-bit set operation
or after a sequence of lock-bit set operations.
Write FFH after the last lock-bit set operation to place device in
read array mode.
Set Lock-Bit
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data(See Above)
SR.3=
1
V PP Range Error
Bus
Operation
Standby
Command
Comments
Check SR.3
1=V PP Error Detect
Check SR.1
0
1
Standby
1=Device Protect Detect
RP#=V IH
(Set Master Lock-BIt Operation)
RP#=V IH , Master Lock-Bit is Set
SR.1=
Device Protect Error
(Set Block Lock-BIt Operation)
0
Standby
Check SR.4,5
Both 1=Command
Sequence Error
SR.4,5=
1
Command Sequence
Error
Standby
Check SR.4
1=Set Lock-Bit Error
0
SR.5,SR.4,SR.3 and SR.1 are only cleared by the Clear Status
Register command in cases where multiple lock-bits are set before
1
full status is checked.
SR.4=
Set Lock-Bit Error
If error is detected, clear the Status Register before attempting
retry or other error recovery.
0
Set Lock-Bit Successful
Figure 9. Set Block and Master Lock-Bit Flowchart
Rev. 1.3
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